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The SS logic input is the chip select input. This input is used
when multiple devices share the serial bus. Drive the SS input
low for the entire data transfer operation. Bringing SS high
receives the last bit, it sets the SS and SCLK lines high, and the
then be initiated by returning the SS logic input to low. However,
master sets the SS /HSA pin low and begins sending one byte,
master sets the SS /HSA pin low and begins sending one byte,
are used in the I 2 C protocol. Bit 0 (read/ write ) of the address byte
used in the I 2 C protocol. Bit 0 (read/ write ) of the address byte must
bit is trans-mitted, the master sets the SS and SCLK lines high at
Data Sheet
E
A A
E
A A
E
A A
during a data transfer operation aborts the transfer and places
the serial bus in a high impedance state. A new transfer can
E
A A
because aborting a data transfer before completion leaves the
accessed register in a state that cannot be guaranteed, the value of a
register should be verified by reading it back each time it is written.
The protocol is similar to the protocol used with the I 2 C interface.
SPI Read Operation
The read operation, using the SPI interface, initiates when the
E
A A
representing the address of the ADE7816 , on the MOSI line. The
master sets data on the MOSI line starting with the first high-to-
low transition of SCLK. The ADE7816 SPI samples data on the
low-to-high transitions of SCLK. The most significant seven bits
of the address byte can have any value, but, as good programming
practice, they should be different from 0111000b, the seven bits
E
A A
be set to 1 for a read operation. Next, the master sends the 16-bit
address of the register to be read. After the ADE7816 receives the
last address bit of the register on a low-to-high transition of SCLK,
SS
SCLK
15 14
ADE7816
it begins to transmit its contents on the MISO line when the next
SCLK high-to-low transition occurs; thus, the master can sample
the data on a low-to-high SCLK transition. After the master
E
A A
communication ends. The data lines, MOSI and MISO, go into
SPI Write Operation
The write operation, using the SPI interface, initiates when the
E
A A
representing the address of the ADE7816 , on the MOSI line.
The master sets data on the MOSI line, starting with the first high-
to-low transition of SCLK. The SPI samples data on the low-to-
high transitions of SCLK. The most significant seven bits of the
address byte can have any value, but, as a good programming
practice, they should be different from 0111000b, the seven bits that
E
A A
must be 0 for a write operation. Next, the master sends the 16-
bit address of the register that is written and the 32-, 16-, or 8-bit
value of that register without losing any SCLK cycle. After the last
E
A A
the end of the SCLK cycle and the communication ends. The data
lines, MOSI and MISO, go into a high impedance state (see
1 0
MOSI
MISO
0 0 0 0 0 0 0 1
REGISTER ADDRESS
31 30
1 0
REGISTER VALUE
Figure 41. SPI Read Operation of a 32-Bit Register
SS
SCLK
15 14
1 0 31 30
1 0
MOSI
0 0 0 0 0 0 0 0
REGISTER
ADDRESS
REGISTER VALUE
Figure 42. SPI Write Operation of a 32-Bit Register
Rev. A | Page 33 of 48
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